The invention relates generally to integrated circuit and other electrical interconnection network fabrication and more particularly to the planarization of layers to produce a sufficiently flat topography in fabricating a multilevel structure.
Multilevel interconnect schemes for integrated circuits generally require one or more planarization steps, in order to maintain an acceptably flat topography for lithography and thin-film step coverage on the higher levels. Traditional approaches have involved planarization of the interlevel insulation (dielectric) layers, either by spin-on application (e.g, polyimide), or by reflow (e.g., phosphosilicate glass).
The fabrication of multilevel VLSI circuits often requires the use of thin-film planarization procedures. The need is particularly acute to achieve wafer-scale integration; an efficient, high-power wafer-scale integrated system might require four levels of interconnect plus two or more ground or power planes. The most severe topographic problems occur around stacked vias, where a connection extends from the bottom interconnect level to the top level.
Planarization techniques have conventionally involved smoothing the dielectric between the metal layers. Spinning on polyimide as the dielectric is often used to achieve planarity. Other dielectric planarization techniques use bias sputter etching, and still others use photoresist to planarize and then plasma back-etch to the underlying SiO.sub.2. Phosphosilicate glass flow can be achieved by furnace heating. Yet another planarization technique uses a scanning cw laser to rapidly flow phosphosilicate glass. None of these techniques will planarize a stacked (nested) via, because the dielectric must be removed from the contact area between each level, resulting in a large thickness deficiency at the via.
A high performance VLSI wafer scale multilevel interconnect system is desirable. This system should be compatible with bi-polar logic technology, i.e., provide high current drive capability and high power. It will often be necessary to provide power, ground, clock and reference voltage planes, especially for ECL technology, to provide low ohmic drops and reduced cross talk. Gold metallization is preferred for low electrical resistance; however, silver and aluminum may also be desirable. A SiO.sub.2 dielectric is preferred for the reliability and thermal tolerance; glass or other dielectrics are also useful. The system must provide multiple levels, e.g., five or more, with some vias extending from top to bottom.
Accordingly it is an object of the invention to provide a method for producing an electrical interconnection network.
It is an also an object of the invention to planarize the levels in a multilevel VLSI circuit.
It is a further object of the invention to produce planarized multilevel electrical interconnection network structures.
It is another object of the invention to produce multilevel VLSI circuit structures having power, ground and/or reference voltage planes.
It is yet another object of the invention to provide a method of producing multiple levels, as many as five or more, with vias extending between various levels, including from top to bottom.